Expand description
A library to parse the x86 CPUID instruction, written in rust with no external dependencies. The implementation closely resembles the Intel CPUID manual description. The library works with no_std.
Example
use raw_cpuid::CpuId;
let cpuid = CpuId::new();
if let Some(vf) = cpuid.get_vendor_info() {
assert!(vf.as_str() == "GenuineIntel" || vf.as_str() == "AuthenticAMD");
}
let has_sse = cpuid.get_feature_info().map_or(false, |finfo| finfo.has_sse());
if has_sse {
println!("CPU supports SSE!");
}
if let Some(cparams) = cpuid.get_cache_parameters() {
for cache in cparams {
let size = cache.associativity() * cache.physical_line_partitions() * cache.coherency_line_size() * cache.sets();
println!("L{}-Cache size is {}", cache.level(), size);
}
} else {
println!("No cache parameter information available")
}
Platform support
CPU vendors may choose to not support certain functions/leafs in cpuid or only support them partially. We highlight this with the following emojis throughout the documentation:
- ✅: This struct/function is fully supported by the vendor.
- 🟡: This struct is partially supported by the vendor, refer to individual functions for more information.
- ❌: This struct/function is not supported by the vendor. When queried on this platform, we will return None/false/0 (or some other sane default).
- ❓: This struct/function is not supported by the vendor according to the manual, but the in practice it still may return valid information.
Note that the presence of a ✅ does not guarantee that a specific feature will exist for your CPU – just that it is potentially supported by the vendor on some of its chips. You will still have to query it at runtime.
Modules
- Uses Rust’s
cpuid
function from thearch
module.
Macros
- Macro which queries cpuid directly.
Structs
- Processor Power Management and RAS Capabilities (LEAF=0x8000_0007).
- Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).
- Iterates over cache information (LEAF=0x02).
- Information about an individual cache in the hierarchy.
- Iterator over caches (LEAF=0x04).
- The main type used to query information about the CPU we’re running on.
- Low-level data-structure to store result of cpuid instruction.
- Deterministic Address Translation Structure
- Deterministic Address Translation Structure Iterator (LEAF=0x18).
- Direct cache access info (LEAF=0x09).
- EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section
- Structured Extended Feature Identifiers (LEAF=0x07).
- Extended Processor and Processor Feature Identifiers (LEAF=0x8000_0001)
- ExtendedState subleaf structure for things that need to be restored.
- Information for saving/restoring extended register state (LEAF=0x0D).
- Yields ExtendedState structs.
- Information about topology (LEAF=0x0B).
- Gives information about the current level in the topology.
- Processor and Processor Feature Identifiers (LEAF=0x01).
- Information about Hypervisor (LEAF=0x4000_0001)
- L1 Cache and TLB Information (LEAF=0x8000_0005).
- L2/L3 Cache and TLB Information (LEAF=0x8000_0006).
- L2 Cache Allocation Technology Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=2).
- L3 Cache Allocation Technology Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=1).
- Information about L3 cache monitoring.
- Memory Bandwidth Allocation Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=3).
- Encrypted Memory Capabilities (LEAF=0x8000_001F).
- Information about how monitor/mwait works on this CPU (LEAF=0x05).
- Info about performance monitoring – how many counters etc. (LEAF=0x0A)
- Performance Optimization Identifier (LEAF=0x8000_001A).
- Processor name (LEAF=0x8000_0002..=0x8000_0004).
- Processor Capacity Parameters and Extended Feature Identification (LEAF=0x8000_0008).
- Processor Frequency Information (LEAF=0x16).
- Processor Serial Number (LEAF=0x3).
- Processor Topology Information (LEAF=0x8000_001E).
- Intel Processor Trace Information (LEAF=0x14).
- Quality of service enforcement information (LEAF=0x10).
- Intel Resource Director Technology RDT (LEAF=0x0F).
- Intel SGX Capability Enumeration Leaf (LEAF=0x12).
- Iterator over the SGX sub-leafs (ECX >= 2).
- Iterator for SoC vendor attributes.
- A vendor brand string as queried from the cpuid leaf.
- SoC vendor specific information (LEAF=0x17).
- Information about the SVM features that the processory supports (LEAF=0x8000_000A).
- Query information about thermal and power management features of the CPU (LEAF=0x06).
- TLB 1-GiB Pages Information (LEAF=0x8000_0019).
- Time Stamp Counter/Core Crystal Clock Information (LEAF=0x15).
- Vendor Info String (LEAF=0x0)
Enums
- Info about cache Associativity.
- What type of cache are we dealing with?
- Info about a what a given cache caches (instructions, data, etc.)
- Deterministic Address Translation cache type (EDX bits 04 – 00)
- Where the extended register state is stored.
- What kidn of extended register state this is.
- Identifies the different Hypervisor products.
- Intel SGX EPC Enumeration Leaf
- What type of core we have at this level in the topology (real CPU or hyper-threaded).
Constants
- This table is taken from Intel manual (Section CPUID instruction).